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HD74LV2G74A
Single D-type Flip Flops with Preset and Clear
REJ03D0097-0500 (Previous: ADE-205-346D) Rev.5.00 Apr 07, 2006
Description
The HD74LV2G74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.
Features
* The basic gate function is lined up as Renesas uni logic series. * Supplied on emboss taping for high-speed automatic mounting. * Electrical characteristics equivalent to the HD74LV74A Supply voltage range : 1.65 to 5.5 V Operating temperature range : -40 to +85C * All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) * Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V) * All the logical input has hysteresis voltage for the slow transition. * Ordering Information
Part Name Package Type Package Code (Previous code) PVSP0008KA-A (TTP-8DBV) US Package Abbreviation Taping Abbreviation (Quantity) E (3,000 pcs / Reel)
HD74LV2G74AUSE SSOP-8 pin
Outline and Article Indication
* HD74LV2G74A
Index band Lot No.
YMW L74
SSOP-8 Marking
Y : Year code (the last digit of year) M : Month code W : Week code
Rev.5.00 Apr 07, 2006 page 1 of 8
HD74LV2G74A
Function Table
Inputs PRE L H L H H H CLR H L L H H H CLK X X X D X X X H L X Q H L H *1 H L Q0 Outputs Q L H H *1 L H Q0
H : High level L : Low level X : Immaterial : Low to high transition : High to low transition Q0 : The level of Q immediately before the input conditions shown in the above table are determined. Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously.
Pin Arrangement
CLK
1
8
VCC
D
2
7
PRE
Q
3
6
CLR
GND
4
5
Q
(Top view)
Rev.5.00 Apr 07, 2006 page 2 of 8
HD74LV2G74A
Absolute Maximum Ratings
Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation *3 at Ta = 25C (in still air) Storage temperature Notes: Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 25 50 200 -65 to 150 Unit V V V mA mA mA mA mW C Test Conditions
Output : H or L VCC : OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOL Min 1.65 0 0 -- -- -- -- -- -- -- -- 0 0 0 0 -40 Max 5.5 5.5 VCC 1 2 6 12 -1 -2 -6 -12 300 200 100 20 85 Unit V V V mA Conditions
IOH
Input transition rise or fall rate
t / v
ns / V
VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
Operating free-air temperature
Ta
C
Note: Unused or floating inputs must be held high or low.
Rev.5.00 Apr 07, 2006 page 3 of 8
HD74LV2G74A
Logic Diagram
PRE CLK C C C Q
TG C C C
C
D
TG
TG
TG Q
C CLR
C
C
Electrical Characteristics
Ta = -40 to 85C
Item Input voltage Symbol VCC (V) * Min VIH 1.65 to 1.95 VCCx0.75 2.3 to 2.7 VCCx0.7 3.0 to 3.6 VCCx0.7 4.5 to 5.5 VCCx0.7 VIL 1.65 to 1.95 -- 2.3 to 2.7 -- 3.0 to 3.6 -- 4.5 to 5.5 -- VH 1.8 -- 2.5 -- 3.3 -- 5.0 -- VOH Min to Max VCC-0.1 1.65 1.4 2.3 2.0 3.0 2.48 4.5 3.8 VOL Min to Max -- 1.65 2.3 3.0 4.5 Input current Quiescent supply current Output leakage current Input capacitance IIN ICC IOFF CIN 0 to 5.5 5.5 0 3.3 -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- 0.25 0.30 0.35 0.45 -- -- -- -- -- -- -- -- -- -- -- -- -- 2.5 Max -- -- -- -- VCCx0.25 VCCx0.3 VCCx0.3 VCCx0.3 -- -- -- -- -- -- -- -- -- 0.1 0.3 0.4 0.44 0.55 1 10 5 -- A A A pF Unit V Test condition
Hysteresis voltage
V
VT+ - VT-
Output voltage
V
IOH = -50 A IOH = -1 mA IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 1 mA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0
VIN or VO = 0 to 5.5 V
VIN = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.5.00 Apr 07, 2006 page 4 of 8
HD74LV2G74A
Switching Characteristics
VCC = 1.8 0.15 V
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL
Ta = 25C Min Typ Max Ta = -40 to 85C Min Max
Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
30 20 -- -- -- -- 13.0 9.0 0.5 12.0 12.0
60 40 16.3 17.9 21.6 24.5 -- -- -- -- --
-- -- 27.0 29.0 34.0 39.5 -- -- -- -- --
20 15 1.0 1.0 1.0 1.0 14.0 9.0 0.5 13.0 13.0
-- -- 29.0 32.0 36.5 42.5 -- -- -- -- --
Setup time Hold time Pulse width
tsu th tw
ns ns ns
PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK D PRE or CLR inactive PRE or CLR "L" CLK "H" or "L"
VCC = 2.5 0.2 V
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL
Ta = 25C Min Typ Max Ta = -40 to 85C Min Max
Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
50 30 -- -- -- -- 8.0 7.0 0.5 8.0 8.0
100 70 9.8 11.1 13.0 14.2 -- -- -- -- --
-- -- 14.8 16.4 17.4 20.0 -- -- -- -- --
40 25 1.0 1.0 1.0 1.0 9.0 7.0 0.5 9.0 9.0
-- -- 17.0 19.0 20.0 23.0 -- -- -- -- --
Setup time Hold time Pulse width
tsu th tw
ns ns ns
PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK D PRE or CLR inactive PRE or CLR "L" CLK "H" or "L"
VCC = 3.3 0.3 V
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL
Ta = 25C Min Typ Max Ta = -40 to 85C Min Max
Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
80 50 -- -- -- -- 6.0 5.0 0.5 6.0 6.0
140 90 6.9 7.9 9.2 10.2 -- -- -- -- --
-- -- 12.3 11.9 15.8 15.4 -- -- -- -- --
70 45 1.0 1.0 1.0 1.0 7.0 5.0 0.5 7.0 7.0
-- -- 14.5 14.0 18.0 17.5 -- -- -- -- --
PRE/CLR CLK PRE/CLR CLK
Q or Q Q or Q
Setup time Hold time Pulse width
tsu th tw
ns ns ns
D PRE or CLR inactive PRE or CLR "L" CLK "H" or "L"
Rev.5.00 Apr 07, 2006 page 5 of 8
HD74LV2G74A VCC = 5.0 0.5 V
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL
Ta = 25C Min Typ Max Ta = -40 to 85C Min Max
Unit MHz ns
Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
FROM (Input)
TO (Output)
130 90 -- -- -- -- 5.0 3.0 0.5 5.0 5.0
180 140 5.0 5.6 6.6 7.2 -- -- -- -- --
-- -- 7.7 7.3 9.7 9.3 -- -- -- -- --
110 75 1.0 1.0 1.0 1.0 5.0 3.0 0.5 5.0 5.0
-- -- 9.0 8.5 11.0 10.5 -- -- -- -- --
Setup time Hold time Pulse width
tsu th tw
ns ns ns
PRE/CLR Q or Q CLK PRE/CLR Q or Q CLK D PRE or CLR inactive PRE or CLR "L" CLK "H" or "L"
Operating Characteristics
CL = 50 pF
Item Power dissipation capacitance Symbol CPD VCC (V) 3.3 5.0 Min -- -- Ta = 25C Typ 13.0 14.0 Max -- -- Unit pF Test Conditions f = 10 MHz
Test Circuit
VCC Input PRE D Input Q CL Output Q VCC
Pulse Generator Zout = 50
Pulse Generator Zout = 50
CLK CLR
Q CL
Output Q
Notes: 1. CL includes probe and jig capacitance. 2. Test is put into the each flip flops.
Rev.5.00 Apr 07, 2006 page 6 of 8
HD74LV2G74A
* Waveform - 1
tr 90 % 50 % 10 % t su th 90 %
tf VCC 10 % 0V
Timming input
Data input
VCC 50 % tw VCC 50 % 0V
Input
50 %
50 % 0V
* Waveform - 2
tr 90 % 50 % 90 % 50 %
tf VCC 10 % t PLH t PHL 0V
Input 10 %
VOH Same-phase output t PHL 50 % t PLH VOH Opposite-phase output 50 % 50 % VOL 50 % VOL
Notes: 1. Input waveform : PRR 1 MHz, Zo = 50 , tr 3 ns, tf 3 ns. 2. The output are measured one at a time with one transition per measurement.
Rev.5.00 Apr 07, 2006 page 7 of 8
HD74LV2G74A
Package Dimensions
JEITA Package Code P-VSSOP8-2.3x2-0.50 RENESAS Code PVSP0008KA-A Previous Code TTP-8DB/TTP-8DBV MASS[Typ.] 0.010g
D 1.5 0.2 8 5 F
bp b1
c1 HE E
Terminal cross section
c
1 e
4 bp
( 0.17 )
L1
Reference Dimension in Millimeters Symbol
Detail F
Min Nom Max D 1.8 2.0 2.2 E 2.2 2.3 2.4 A2 0.6 0.7 0.8 A1 0.1 0 A bp 0.15 0.22 0.3 b1 0.20 c 0.08 0.13 0.23 c1 0.11 HE 2.8 3.1 3.4 e (0.5) x y Z L L1 (0.4)
Rev.5.00 Apr 07, 2006 page 8 of 8
A1
A2
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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